Gate and high-k dielectric
Thakur said: “As long as we imagine the transistor and its surroundings, we can find several basic structures. The first is the most basic gate stack structure. In the gate stack structure, we usually use silicon oxide. Under the changed circumstances, through the miniaturization process, the basic performance of transistors has achieved an annual growth rate of 17%. Now, we have introduced a new material-silicon nitride oxide, the dielectric is still amorphous material, and silicon oxide is still its basic Composition.” Logic products have adopted silicon nitride oxide technology since the 130nm process, while other products depend on changes in design rules. This change is ongoing. While applying the silicon nitride oxide material, the polysilicon electrode structure remains unchanged.
The traditional silicon oxide/standard doped (sometimes ion implanted) polysilicon gate structure has gradually transitioned to a metal silicide and then a nitride oxide structure. “The 65nm process will begin to use high-k dielectrics.” Thakur said, “At that time, chip manufacturers will consider using metal gates or highly doped electrodes to replace polysilicon electrodes. In fact, logic product suppliers have begun to discuss metal gates. Extremely problematic. From the perspective of gate stacking, the use of metal gates is already a very obvious trend.”
Another major change from the 65nm process is the change of the silicon substrate. Thakur said: “We already have wafer surface epitaxy and overall epitaxy technology, and we have begun to consider the use of improved source/drain structure, which can introduce a new function in the epitaxial structure: selective process. In the past two decades, we have never It has used selective tungsten and selective FSG processes. But like DRAM, it is indeed feasible to use selective epitaxy to improve the source/drain structure. The traditional epitaxy technology is very mature, and you can add germanium to increase the drive current.”
Logic products have a fancy SOI substrate. Although SOI technology still has some problems to be solved, SOI has obvious heat dissipation advantages for logic products. For device manufacturers to adopt a certain technology, it must have the advantages of low cost and high performance. When engineers do their best to reach the physical limits of existing processes, changes in certain aspects are inevitable. It is uncertain whether the 45nm process will adopt SOI, but it is generally believed that the 32nm process will adopt SOI. Thakur said: “The problem is how to make ultra-thin junctions. Starting from the 65nm process, junctions have become very shallow, so problems related to channels will begin to show up. First, the junction is ion implanted, and then the junction is formed. In the past The heat treatment method has been unacceptable. This will lead to a change in the types of dopants that can be used because we require higher conductivity in limited junctions.” As for junction formation, people will continue to try some traditional methods such as RTP For heat treatment and reduce thermal budget, perhaps laser heating or some new spike annealing methods will be used.
Bob Soave, a strategy expert at Tokyo Electron Ltd., pointed out that people have been discussing advanced gate stack structures for almost ten years. “This is because people are worried that the shrinking process will make the SiO2 layer thinner and eventually lead to excessive leakage current. It was once predicted that the process below 0.18um can no longer use SiO2. However, the use of SiO2 has exceeded anyone’s expectations, and it is also It can last for a period of time. Nevertheless, the continued scaling has almost reached the physical limit of existing materials, so we need to replace SiO2 with other dielectric and electrode materials.”
These materials may be obtained through thermal or chemical reactions, and they are not as simple as silicon oxidation or silane deposition to prepare polysilicon. Soave said, “Because the chemical reaction is relatively complex, and we are relatively unclear about the reaction mechanism, the main problem is how to control the composition and electrical properties of the membrane through the process, and develop a repetitive reactor for production. And integrate it into the production line.”
Michael Grant, vice president of TEL’s Thermal Systems Division, found some important issues when considering high-k dielectrics and metal gates. “First, basic materials and scientific research, and then integration issues. Two years ago, if you consulted the major U.S. logic device manufacturers about their 65nm process gate strategy, they all expected to introduce high-k dielectrics and metals. Trial production of gate products. This situation has been going on for two years. Now they are more cautious and think it is possible to adopt this structure at the end of the 65nm process era, and 45nm is the most likely period to adopt this structure. At present, the This technology still has many integration-related problems to be solved.”